In the processing of communication signals there is a need to convert the received signal from analog to digital form as early as possible in the processing of the signal to allow the use of sophisticated filtering, demodulation and other processing tasks that are better accomplished in the digital domain. This need places requirements on the analog to digital interface to have an input bandwidth substantially equal to that of the received signal, to have a dynamic range sufficient to accommodate the expected amplitude variability of the received signal, and to not substantially increase the noise or spurious signal content of the resulting digital signal.
The sampling frequency used in the analog to digital conversion process is related to the analog signal bandwidth by the Nyquist rate well known to those skilled in the art. If a signal is band limited to a bandwidth, W, it can be substantially reproduced in digital form if it is sampled at a rate, F.sub.s, where F.sub.s .gtoreq.2 W. Generally, some level of over sampling is used with F.sub.s being one and one half or more times the minimum sampling rate.
Single component or similar configuration analog to digital converters are commercially available. However, these devices generally do not have sufficiently high sampling rate capability to meet the wide bandwidth requirements desired in communication systems. An intrinsic design characteristic is that devices with greater dynamic range are more limited in sampling rate and consume a larger amount of power. In the past a variety of schemes have been developed to combine two or more analog to digital converter (ADC) components to achieve the desired increase in bandwidth but the resulting design must include methods to eliminate variations in ADC device parameters. These components exhibit small but finite variations from device to device in gain, linearity, and the offset of the output at zero signal input, as well as shifts in these parameters due to changes in ambient temperature and aging. Compensation for these variations must be accomplished before the digital signals from a plurality of these components are interlaced to form a single output.
An ADC should demonstrate a linear relationship between the amplitude of the analog input and that of the digital output. The digital output should also faithfully reproduce the polarity of the analog input. This relationship can be described by the well known mathematical description of a straight line. EQU Y=m.times.X+b
where: Y represents the digital output, X represents the analog input, m represents the gain of the transfer function, and b is the offset error in the output with zero as the analog input. Typical commercially available ADCs exhibit some small device to device variations in the value of m and exhibit small but finite values for b. Further, such ADCs may exhibit some non-linearity in the transfer function which can be expressed by the addition of higher order X.sup.2, X.sup.3, etc., terms to the equation. If a plurality of ADCs are combined without compensation for device to device differences, substantial degradation in the dynamic range of the multi-ADC system will occur. For example, if at zero volts analog input one ADC generates a digital output of plus one last significant bit (LSB), the other ADC output is minus one LSB, and these errors were not compensated for, the total dynamic range of the concatenated ADC outputs would be reduced by two bits or 12 dB. Differences in gain and non-linearities from ADC to ADC must also be removed to prevent the introduction of significant spurious signals into the resulting digital data stream.
FIG. 1 shows an example of a prior art wideband analog to digital (A/D) conversion system, using commercially available converter components, which comprises an input stage 10, a gain and offset adjustment stage 16, a conversion stage 30, and a processor stage 38. The system receives wideband analog signals 11 and supplies their digital equivalent to associated digital signal processing circuits (not shown) via the digital interface 39.
The input stage 10 comprises a switching array and a reference voltage source 12 for calibrating the system, and an antialiasing filter 14. In response to control inputs 37 from the processor stage 38, the switching array selects either the analog input 11, an analog ground reference, or the reference voltage as the signal 15 to be sent to the antialiasing filter 14. The reference voltage source provides a substantially constant value voltage to be used for calibrating the A/D conversion system. The prior art example shown in FIG. 1 is intended to produce the digital equivalent of analog signals within a bandwidth of 0 to 40 MHz. The purpose of the antialiasing filter is to substantially remove from its input signal 15 any signal components outside that bandwidth before supplying the band limited signal 17 to the following gain and offset adjustment stage 16.
The gain and offset adjustment stage 16 comprises two identical channels. The first channel shown in FIG. 1 comprises a substantially linear operational amplifier 18 capable of receiving gain and offset adjustments, and two DACs 20 and 22 which provide the gain and offset adjustment control voltages. The output 21 of the channel is a faithful reproduction of the input signal 17 with the exception that the amplitude differs in accordance with the gain adjustment and its zero reference is offset in accordance with the offset control voltage. Operational amplifier 24 and DACs 26 and 28 make up the second channel of the gain and offset adjustment stage 16 and function in the same manner as components 18, 20 and 22, respectively, of the first channel.
Conversion stage 30 comprises two commercially available ADC components 32 and 34. In the prior art example of FIG. 1, the ADC components are assumed to have the capability to operate at a sampling rate of 60 megasamples per second or less, and to produce a 10 bit digital output representing the amplitude of each input sample. The two ADCs are supplied from the processor stage 38 clock signals with a phase relationship of 180 degrees at a frequency of 60 MHz. The combination of the two ADCs and the phasing of the clock signals results in an effective sampling rate of 120 MHz when the ADC outputs are interleaved.
The processor stage 38 comprises either an application specific integrated circuit or simply part of the resources of the host processor to which this A/D interface is attached. Functions performed by processor stage 38 comprise (1) control of the switching array 12 in the input stage 10, (2) computation of the gain and offset error control signals 25 and 27 and their subsequent supply to the DACs 20, 22, 26 and 28 in the gain and offset adjustment stage 16, (3) generation of sampling clock signals, the proper phasing of these signals, and the transmission of these clock signals to ADCs 32 and 34 by way of digital busses 29 and 31, (4) the reception of the signal samples in digital form from ADCs 32 and 34 by way of digital busses 29 and 31, and their concatenation into a single digital data stream, and (5) the filtering of the interlaced data stream to significantly reduce noise and spurious signal components introduced into the data by the conversion process.
The offset error portion of the control signals 25 and 27 are computed by the process of commanding the switching array 12 to switch the antialiasing filter input 15 to the analog ground reference. The resulting digital signal outputs of the ADCs on digital busses 29 and 31 are compared with the expected output for a zero input, error signals are generated for each ADC that will result in their outputs equaling zero inputs, and these error signals are stored and then supplied to DACs 20 and 26 during the conversion of analog input signals. In a similar manner the gain correction portion of the control signals 25 and 27 are computed by commanding the switching array 12 to provide an appropriate known value reference voltage to the antialiasing filter input 15. The resulting digital signal outputs of the ADCs are compared to expected outputs for this voltage, gain correction signals for each converter are generated which result in their output having the proper value for the reference voltage input, and these gain correction signals are stored and supplied to DACs 22 and 28 for use during analog to digital signal conversion.
Difficulties with the prior art arrangement shown in FIG. 1 are that it introduces an extra stage, gain and offset adjustment stage 16, in the analog signal path which adds its own errors into the analog signals being processed. Also, gain and offset adjustment stage 16 adds the relatively significant expense of the highly linear operational amplifiers 18 and 24, and the four DACs 20, 22, 26, and 28. The prior art configuration can only correct for gain at one reference point; it cannot correct for non-linearities in the combined transfer functions of the linear operational amplifiers 18 and 24, and the ADCs 32 and 34.
Hence, what is needed is an improved apparatus and method for compensating offset and gain errors in combined ADCs.